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Intel’s Core i7

Jason Lopez — Thu, 13 Nov 2008 23:30:07 +0000

The Core i7 microprocessor (built on Intel’s Nehalem microarchitecture) represents a major advance in computing to enable chips to handle more data. In this video podcast, Ronak Singhal, a lead architect on Nehalem, says the chip design is an overhaul–the internal core has been changed significantly for added performance, as well as for better energy efficiency.

“We’ve put in features such as Turbo Boost Technology, our integrated power gate, an integrated memory controller, and Hyper-Threading,” he says. The effort took about five years and required thousands of engineers.

“Building this microprocessor brings a lot of people together, like architects, micro architects, the design teams,” commented Rani Borkar, vice president of Intel’s Digital Enterprise Group. “As you get into the development phases, working with the process technology, it’s a mind-boggling effort that requires a lot of teamwork across the board.”

This video takes you into Intel’s labs to meet some of the researchers behind the Core i7.

Tags: Core i7, microprocessor, Intel, Nehalem, microarchitecture, Ronak Singhal, chip design, Turbo Boost Technology, Hyper-Threading, Rani Borkar, energy efficiency, Energy Smart, Francois Piednoel, Regina Wu, gaming

Intel Tick-Tock Strategy - What it Means

editor — Fri, 12 Sep 2008 20:13:17 +0000

Driving technology innovation on a reliable and predictable timeline, Intel developed a model designed to deliver ongoing innovation. Referred to as our tick-tock model, Intel has successfully alternated and delivered the next generation of silicon technology as well as new processor microarchitecture year after year.

Intel CIO Diane Bryant shares how, during the “Tick,” Intel delivers new silicon process technology, dramatically increasing transistor density while enhancing performance and energy efficiency within a smaller, more refined version of our existing microarchitecture.

In the second year, the “Tock” delivers entirely new processor microarchitecture to optimize the value of the increased number of transistors and technology updates now available.

If you’re an investor, you can stay on top of all the ways Intel pushes the boundaries of innovation, making news in technology, manufacturing, education, culture and social responsibiliy. Learn more about the rhythm of Intel’s advancing silicon technology and what it means for your business, your investment, and you.

Tags: Intel, Tick-Tock, Chip Design, Chip Manufacturing, 45nm, Diane Bryant, Nehalem, Core i7

Inside IDF: Nehalem Microarchitecture

Jason Lopez — Wed, 23 Jul 2008 05:39:52 +0000

The Intel Developer Forum has become a major event on the technology industry calendar with keynotes that make international headlines. But at the heart of IDF are the sessions where developers get access to the details of new products and science from the world’s biggest chipmaker. This podcast is an excerpt from IDF Shanghai 2008. It’s an example from the session “Inside Intel Next Generation Nehalem Microarchitecture.”

Tags: IDF, Intel, Intel Developer Forum, Shanghai, Microarchitecture , Nehalem

IDF 2008 San Francisco

Jason Lopez — Wed, 16 Jul 2008 20:36:27 +0000

The Intel Developer Forum has evolved into one of the most important technology events of the year. For anyone making hardware and software, IDF provides a way to learn about critical advances in chip design, and it gives Intel the opportunity to get feedback from developers. For the rest of the world, IDF is where Intel’s latest thinking comes to light about the way people use computers and how to design better chips. At the upcoming IDF, Intel will give insights into next generation microarchitecture, mobile Internet devices, nettops and netbooks, consumer electronics, and embedded computing. In this video podcast, we take a brief look back at past IDFs leading up to this August 19-21 in San Francisco’s Moscone Center West.

Tags: Intel Developer Forum, IDF, Intel, microarchitecture, mobile Internet devices

Nehalem Microarchitecture - Intel Chip Chat - Episode 27

editor — Wed, 04 Jun 2008 16:08:23 +0000

In this audio podcast, Nehalem lead architect Ronak Singhal discusses the significant performance and power improvements of Intel’s latest leap in microarchitectural design. The technology has significant implications for dynamic scalability, design and performance scalability, simultaneous multi-threading, scalable shared memory and multi-level shared caching. The ground-up design takes advantage of the hafnium-based Intel 45nm hi-k metal gate silicon technology, and is the first to introduce Intel QuickPath technology.

Tags: Nehalem, Ronak Singhal, multi-threading, scalable, hafnium, 45nm, QuickPath, microarchitecture

Intel Lowers Energy Costs for High Performance Computing

editor — Tue, 20 May 2008 15:00:04 +0000

The current uptake in high performance computing means mostly good things, but it also comes with a few built-in challenges. The paradox of this particular progress is this: when you scale hardware, you oftentimes scale power consumption, right along with it. That’s where Intel’s Shesha Krishnapura has some good news to share, in this podcast speaking with The Register’s Tim Phillips. Says Krishnapura, “In the past, that power relationship has existed. But with Intel’s core microarchitecture platform, the power holds constant while performance climbs.”

Intel is working to improve the performance-per-watt characteristics of HPC systems. The effort is important, as Xeon-based servers dominate the Top 500 supercomputers list and the clusters used by businesses for their most demanding jobs.

Fist of all, Intel’s throughput-per-rack measurement helps illustrate the point when Intel 45nm-based quad-core processors run at similar power levels as dual-core processors, while offering twice the number of processing cores per server. Add Intel’s switch to higher density memory like 4GB memory modules instead of 2GB modules — the 4GB run at similar power envelope — and it’s clear where Intel is holding a fairly stable power envelope and still seen what Krishnapura calls, “a substantial performance increase, year after year.”

Krishnapura is a principal engineer in the Intel Platform and Design Capability Engineering group, driving the internal engineering of High Performance Computing solutions optimized for Tapeout and Design Computing. As an architect of Intel Architecture migration program for Electronic Design Automation, Shesha is responsible for enabling IA-based optimization and adoption in EDA market by enabling application vendors and strategically influencing world-wide semiconductor customers for best-in-class design compute solutions.

Tags: Shesha Krishnapura, Tim Phillips, Xeon, servers, 45nm, High Performance Computing, Tapeout, Design Computing, Intel Architecture, Electronic Design Automation, IA, optimization, HPC, Intel, VTune, Threading Analysis, Intel Performance Libraries, Intel Threading Building Blocks, EDA

Intel’s Xeon Custom-Made for High-Performance Computing

Catherine Girardeau — Sun, 11 Nov 2007 19:00:58 +0000

High-performance computing presents unique challenges in performance, energy efficiency and parallel processing, and Intel has just unveiled a unique solution. The Intel Xeon processors and platforms use an entirely new transistor formula based on the second generation of the Intel Core microarchitecture. Intel’s new high-performance computing (HPC) platform is made possible by technological advancements in the new quad-core Intel Xeon processor 5400 series or dual-core Intel Xeon processor 5200 series, and Intel 5400 chipset. Intel Co-Founder Gordon Moore calls the processors which use Intel’s Hafnium-based High-k metal gate transistor formula and will be manufactured on the company’s 45-nanometer process, the biggest transistor advancement in 40 years.

The new Xeon family continues Intel’s leadership in delivering faster, more energy-efficient processors, with a 38 percent improvement in performance per watt over its predecessor.

Nehalem: Next-Gen Microarchitecture - Intel Chip Chat - Episode 11b

editor — Thu, 20 Sep 2007 02:26:09 +0000

Intel’s next-generation 45nm Hi-k microarchitecture (code named “Nehalem”) is a dynamically scalable microarchitecture that delivers breakthrough energy-efficient performance.

Related Stories: IntelIDF, IntelMooresLaw

Tags: Intel, 45nm, Hi-k, microarchitecture, Nehalem, energy-efficient, IntelIDF, IntelMooresLaw

Live from IDF: Gelsinger Puts Nehalem and Virtualization on Display

Catherine Girardeau — Wed, 19 Sep 2007 03:06:45 +0000

In his keynote today at the Intel Developer Forum in San Francisco, Patrick Gelsinger, senior vice president and general manager of Intel’s Digital Enterprise Group, gave a broad update on Intel’s efforts this year.

In this podcast, Gelsinger covers what he calls the company’s “relentless pursuit of Moore’s Law,” spotlighting Nehalem (that’s the codename for “the first-ever Intel 45 nanometer High-k metal gate next-generation microarchitecture dual processor server,” according to company statements).

He also revealed Intel’s plans to build on the latest roll-out of Intel vPro processor technology with a 2008 release called “McCreary,” which will include new halogen and lead-free 45nm dual and quad-core processors.

Encryption and decryption technology is addressed with Danbury technology (one reaction to which can be found here).

Underscoring the current momentum around virtualization, Gelsinger was joined onstage at one point by John Fowler, executive vice president of Sun Microsystems. A demonstration of Intel Virtualization Technology and Intel Trusted Execution Technology shed some light on how Intel will provide protection for virtual environments in the workstations and desktop PCs of the future.

Check out Pat Gelsinger’s blog for more thoughts from (and after) IDF.

Tags: Intel Developer Forum, Patrick Gelsinger, Digital Enterprise Group, Moore’s Law, Nehalem, 45 nanometer, microarchitecture, dual processor, vPro, McCreary, lead-free, Encryption, decryption, Danbury technology, virtualization, John Fowler

Inside 45nm Hi-k Silicon Innovation - Intel Chip Chat - Episode 7

editor — Mon, 27 Aug 2007 19:58:56 +0000

45nm Program Manager Kaizad Mistry takes you inside the groundbreaking 45nm Hi-k metal gate process technology used in the next generation of Intel Core microarchitecture.

Intel Unveils New 45nm Architecture-Nehalem

Jason Lopez — Thu, 29 Mar 2007 00:27:03 +0000

Intel unveiled the next stages for its new 45 nanometer process technology. The new microarchitecture is code-named Nehalem and represents a major shift in design. The technology is aimed partly at the requirements of next-generation media services over the Internet. Chips based on Nehalem are expected to launch in 2008. At a San Francisco press briefing, PodTech’s Jason Lopez spoke with Intel’s Pat Gelsinger about Nehalem, IDF Beijing and his upcoming blog.

Core Microarchitecture in Servers: Intel’s Kirk Skaugen

editor — Tue, 27 Jun 2006 06:16:51 +0000

Kirk Skaugen is vice president of the Digital Enterprise Group and co-general manager of the Intel Server Platforms Group . In this podcast Skaugen talks about practical applications for Intel’s server and workstation platforms working with Intel’s Core Microarchitecture such as the Xeon 5100.

More info:
IntelStartYourEngines.com

Tags: Kirk Skaugen, Intel, Xeon 5100

Core Microarchitecture in Servers: Intel’s Thomas Kilroy

editor — Tue, 27 Jun 2006 06:05:01 +0000

Tom Kilroy is vice president and general manager of Intel Corporation’s Digital Enterprise Group. He covers computing and communications infrastructure platforms for business. In this podcast he introduces Intel’s new microprocessor for server computers, the first chips built with Intel’s newest Core Microarchitecture, the Xeon 5100.

More info:
IntelStartYourEngines.com

Tags: Tom Kilroy, Intel, Xeon 5100

Intel - Justin Rattner, CTO - Core Microarchitecture, IDF Keynote - 1 of 3 parts

John Furrier — Tue, 07 Mar 2006 18:16:24 +0000

Intel Developer Forum - Justin Rattner, CTO Keynote Part 1 of 3 - March 7, 2006, San Francisco

“Join Justin Rattner for a technology tour de force on the key challenges facing the industry and Intel’s multifaceted response of complete platform solutions - from transistors through software. Justin will highlight recent semiconductor advances for 65nm, Intel’s next-generation michroarchitecture that delivers a common, power-optimized foundation for ultra-light notebooks through high-end servers, platform innovations for enhanced energy-efficiency, and software tools and ecosystem initiatives to enable the threading revolution and unleash the capability of multi-core platforms.”

In this first of three parts of Justin’s keynote he speaks about “core microarchitecture”.

Justin Rattner’s blog